1. Field of the Invention
The invention relates to a tooling method and a semiconductor device formed thereof, and more particularly, to a tooling method utilizing Boolean operations and a semiconductor device fabricated thereof.
2. Description of the Prior Art
Field effect transistors are important electronic devices in the fabrication of integrated circuits, and as the size of the semiconductor device shrinks, fabrications of the transistors and interconnects have to be improved for fabricating transistors with smaller sizes and higher quality.
Conventionally, after forming the transistors, contact plugs are often utilized for interconnection purposes, in which the contact plugs are composed of conducting metals such as tungsten or copper to electrically connect the gate, source, and drain to upper level interconnect layers. Furthermore, silicide layers are often formed over the surface of the gate structure and the source/drain region to improve the Ohmic contact between the contact plugs and the gate structure and the source/drain region. For example, a self-align silicide (salicide) process has been widely utilized to fabricate the silicide layers. The salicide process, after forming a salicide block (SAB) layer over non-salicide regions that are defined by a layout pattern according to a design rule provided from clients, includes steps of disposing a metal layer comprised of cobalt, titanium, or nickel on a source/drain region and a gate structure, and performing a rapid thermal process (RTP), thus the metal layer reacts with the silicon contained within the gate structure and the source/drain region to form a metal silicide.
As mentioned above, the salicide is utilized to reduce contact resistance of diffusion regions in typical logic circuits. However, inferior salicide formation sometimes happens due to incomplete metal layer formation between devices having too narrow device-to-device spacing and thereby inducing high leakage current and hence power supply current test (IDDQ test) failure. It is observed that this phenomenon usually and particularly happens at locations where the device-to-device spacing such as the poly-to-poly spacing is too narrow and without contact.
Therefore, a method capable of preventing abovementioned phenomenon and hence avoiding IDDQ test failure is needed.